Performance Tuning and Reliability Analysis of the Electrostatically Configured Nanotube Tunnel FET with Impact of Interface Trap Charges

被引:2
|
作者
Gupta, Ashok Kumar [1 ]
Raman, Ashish [1 ]
Kumar, Naveen [1 ]
机构
[1] Dr BR Ambedkar Natl Inst Technol, Dept Elect & Commun, VLSI Design Lab, Jalandhar 144011, Punjab, India
关键词
Charge plasma technique (CP); Electrostatic doped technique (ED); Nano-tube TFET (NT-TFET); Linearity parameter; Tunnel field-effect transistors (TFETs); Interface trapped charges (ITCs); RANDOM DOPANT FLUCTUATION; DESIGN; SILICON; TFET; GATE;
D O I
10.1007/s12633-020-00777-8
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
This paper examines, an electrostatically configured Nano-Tube Tunnel Field-Effect Transistor (ED-NTTFET). During the fabrication process, different charges such as fixed charge, oxide trapped charge, and interface trapped charge have been produced at the gate oxide interface. So the effect of positive and negative interface trapped charge (+ITC & -ITC) has been proposed for the first time for electrostatic doped-based Nano-Tube TFET (ED-NTTFET). There are two types of techniques, charge plasma (EP) based technique and electrostatic doped (ED) technique is used to produce the induced charge in the intrinsic channel region. In the charged plasma (CP) technique, the metal work-function is used to produce the induced charge while in the electrostatic doped (ED) technique electrostatic voltage is applied across the source and drain side to produce the induced charge in the intrinsic channel region. Analysis of the various device parameters such as hole/electron concentration, energy diagram, electric field, tunneling rate, driving current, OFF current, ON current, I-ON/I-OFF, threshold voltage, and average sub-threshold slope in the presence of interface trapped charge (ITC). Due to positive interface trapped charge electric field and band to band tunneling rates are improved. So the drain current of the device also improved from the 2.94*10(-5) A/um(2) to 5.35*10(-5)A/um(2). Linearity parameters such as second & third order trans-conductance (g(m2) & g(m3)), second & third order voltage intercept point (VIP2 & VIP3), second & third order harmonics distortions (HD2 & HD3) and intermodulation distortions (IMD) have been discussed. The negative interface trapped charge (-ITC) degrades the linearity parameter of the device and the positive interface trapped charge (+ITC) improves the linearity parameter of the device. The proposed electrostatic doped nano-tube TFET (ED-NTTFET) produced higher cut-off frequency at lowers operating gate voltage.
引用
收藏
页码:4553 / 4564
页数:12
相关论文
共 50 条
  • [41] Impact of interface traps and noise analysis on dual material graded channel CGAA FET: A device reliability
    Mudidhe, Praveen Kumar
    Nistala, Bheema Rao
    MICRO AND NANOSTRUCTURES, 2024, 191
  • [42] Analysis of interface trap charges on RF/analog performances of dual-gate-source-drain Schottky FET for high-frequency applications
    Anusuya, P.
    Kumar, Prashanth
    MULTISCALE AND MULTIDISCIPLINARY MODELING EXPERIMENTS AND DESIGN, 2024, 7 (04) : 3447 - 3455
  • [43] Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability
    Gupta, Sarthak
    Sharma, Dheeraj
    Soni, Deepak
    Yadav, Shivendra
    Aslam, Mohd.
    Yadav, Dharmendra Singh
    Nigam, Kaushal
    Sharma, Neeraj
    MICRO & NANO LETTERS, 2018, 13 (08): : 1192 - 1196
  • [44] Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability
    Gupta S.
    Sharma D.
    Soni D.
    Yadav S.
    Aslam M.
    Yadav D.S.
    Nigam K.
    Sharma N.
    Micro and Nano Letters, 2018, 13 (08): : 1192 - 1196
  • [45] Impact of temperature on analog/RF, linearity and reliability performance metrics of tunnel FET with ultra-thin source region
    Prabhat Singh
    Dharmendra Singh Yadav
    Applied Physics A, 2021, 127
  • [46] Performance Assessment of the Charge-Plasma-Based Cylindrical GAA Vertical Nanowire TFET With Impact of Interface Trap Charges
    Kumar, Naveen
    Raman, Ashish
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (10) : 4453 - 4460
  • [47] Impact of temperature on analog/RF, linearity and reliability performance metrics of tunnel FET with ultra-thin source region
    Singh, Prabhat
    Yadav, Dharmendra Singh
    APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 2021, 127 (09):
  • [48] Reliability Issues of In2O5Sn Gate Electrode Recessed Channel MOSFET: Impact of Interface Trap Charges and Temperature
    Kumar, Ajay
    Tripathi, M. M.
    Chaujar, Rishu
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (03) : 860 - 866
  • [49] Analysis of performance for novel pocket-doped NCFET under the influence of interface trap charges and temperature variation
    Choudhuri, Bijit
    Mummaneni, Kavicharan
    Mummaneni, Kavicharan
    MICROELECTRONICS JOURNAL, 2022, 127
  • [50] Performance analysis of ITCs on analog/RF, linearity and reliability performance metrics of tunnel FET with ultra-thin source region
    Singh, Prabhat
    Yadav, Dharmendra Singh
    APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 2022, 128 (07):