A need of quantum computing: "Reversible logic synthesis of parallel binary adder-subtractor"

被引：0

作者：

Thapliyal, H ^{[1
]}

Srinivas, M ^{[1
]}

Arabnia, HR ^{[1
]}

机构：

[1] Int Inst Informat Technol, Ctr VLSI & Embedded Syst Technol, Hyderabad 500019, Andhra Pradesh, India

来源：

ESA '05: PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS AND APPLICATIONS | 2005年

关键词：

reversible logic; reversible subtractor; reversible parallel binary adder-subtractor;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Earlier research has proved that a finite amount of energy dissipation would occur if the computation is devoid of reversible logic. In the light of this problem, a binary parallel adder-subtractor using reversible logic is proposed. The proposed circuit has the ability to add and subtract two 4-bit binary, numbers depending on the mode bit M This circuit can be generalized for N bit addition and subtraction. The proposed design technique uses minimum number of gates as well as garbage outputs thereby significantly reducing the circuit complexity.

引用

页码：60 / 66

页数：7

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