Low Power Comparator with Offset Cancellation Technique for Flash ADC

The design and analysis of a low power comparator that features an offset cancellation technique has been carried out in this paper. The proposed low power circuit works on a 1 GHz sampling frequency and is developed in 65nm CMOS technology. An offset cancellation technique and a switch are added to the comparator to reduce the offset and kickback noise. The comparator is implemented in a 5-bit Flash Analog to Digital converter (ADC) and the overall measured power consumption from 1 V power supply is 568 mu W. The proposed ADC can convert the analog input to digital output with 4.62 bits ENOB in Nyquist input frequency whilst the SNDR and SFDR are 29.6 dB and 42.4 dB, respectively.