Impact strain engineering on gate stack quality and reliability

被引：69

作者：

Claeys, C. ^{[1
,2
]}

Simoen, E. ^{[1
]}

Put, S. ^{[1
,2
,3
]}

Giusi, G. ^{[4
]}

Crupi, F. ^{[4
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, EE Dept, B-3001 Louvain, Belgium

[3] CEN SCK, B-2400 Mol, Belgium

[4] Univ Calabria, DEIS, I-87036 Arcavacata Di Rende, Italy

来源：

SOLID-STATE ELECTRONICS | 2008年 / 52卷 / 08期

关键词：

silicon-on-insulator (SOI); fully depleted SOI MOSFETs; low-frequency noise; strain engineering; low-field mobility; contact etch stop layer (CESL); strained SOI (sSOI);

D O I：

10.1016/j.sse.2008.04.035

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Strain engineering based on either a global approach using high-mobility substrates or the implementation of so-called processing-induced stressors has become common practice for 90 nm and below CMOS technologies. Although the main goal is to improve the performance by increasing the drive current, other electrical parameters such as the threshold voltage, the multiplication current, the low frequency noise and the gate oxide quality in general may be influenced. This paper reviews the impact of different global and local strain engineering techniques on the gate stack quality and its reliability, including hot carrier performance, negative bias temperature instabilities, time dependent dielectric breakdown and radiation hardness. Recent insights will be discussed and the influence of different strain engineering approaches illustrated. (C) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1115 / 1126

页数：12

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