A Doherty Power Amplifier Design Method for Improved Efficiency and Linearity

A novel Doherty power amplifier (PA) design method enabling high efficiency and high linearity simultaneously is proposed. The output combiner network is treated as a black box, and its parameters, together with the input phase delay, are solved based on given transistor characteristics and design requirements. This opens for new PA solutions with nonconventional Doherty behavior. The increased design space enables new tradeoffs in Doherty PA designs, including solutions with both high efficiency and high linearity simultaneously. A method utilizing the new design space is developed. For verification, a 20-W 2.14-GHz symmetrical gallium nitride high electron mobility transistors Doherty PA is fabricated and measured. The PA obtains an average power added efficiency of 40% and an adjacent power leakage ratio of -41 dBc without any linearization for an 8.6-dB peak to average power ratio 10-MHz-long term evolution signal, at an average output power of 35.5 dBm.