SEU sensitivity of Virtex configuration logic

被引:12
作者
Alderighi, M [1 ]
Candelori, A
Casini, F
D'Angelo, S
Mancini, M
Paccagnella, A
Pastore, S
Sechi, GR
机构
[1] Ist Nazl Astrofis, Ist Astrofis Spaziale & Fis Cosm, I-20133 Milan, Italy
[2] Ist Nazl Fis Nucl, I-35131 Padua, Italy
[3] Sanitas EG Srl, I-20122 Milan, Italy
[4] Univ Padua, Dipartimento Ingn Informaz, I-35131 Padua, Italy
关键词
field programmable gate arrays (FPGA); heavy ion radiation effects; radiation effects; semiconductor device radiation testing; single event effects;
D O I
10.1109/TNS.2005.860741
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a strategy of investigation of SEU upset mechanisms in the configuration logic of Virtex I devices. Measurement procedures specifically addressing configuration logic and a hardware set up for radiation testing are described. The results of a heavy ion radiation test are then presented. Previously unreported failure mechanisms have been observed and classified and their corresponding cross sections measured.
引用
收藏
页码:2462 / 2467
页数:6
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