A Gate-Induced Drain-Leakage Current Model for Fully Depleted Double-Gate MOSFETs

被引：3

作者：

Jin, Xiaoshi ^{[1
]}

Liu, Xi ^{[1
]}

Lee, Jong-Ho ^{[1
]}

机构：

[1] Kyungpook Natl Univ, Sch Elect Engn & Comp Sci, Taegu 702701, South Korea

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 10期

关键词：

Double gate (DG); fully depleted; gate-induced drain leakage (GIDL); MOSFETs; separation of variables;

D O I：

10.1109/TED.2008.2003229

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A gate-induced drain-leakage current model which can avoid the invalidation of 1-D models for fully depleted double-gate MOSFETs was developed based on tunneling theory and the analytical solution of a 2-D Poisson equation. For a given device geometry and a doping concentration, assuming that the drain region was fully depleted, the 2-D Poisson equation is solved using a separation-of-variable technique with appropriate boundary conditions. The results were compared with the data from a 2-D device simulation and showed good agreement.

引用

页码：2800 / 2804

页数：5

共 50 条

[1] Drain current model for nanoscale double-gate MOSFETs
Hariharan, Venkatnarayan
Thakker, Rajesh
Singh, Karmvir
Sachid, Angada B.
Patil, M. B.
Vasi, Juzer
Rao, V. Ramgopal
SOLID-STATE ELECTRONICS, 2009, 53 (09) : 1001 - 1008
[2] Investigation of gate-induced drain leakage (GIDL) current in thin body devices: Single-gate ultra-thin body, symmetrical double-gate, and asymmetrical double-gate MOSFETs
Choi, YK
Ha, D
King, TJ
Bokor, J
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2003, 42 (4B): : 2073 - 2076
[3] Investigation of gate-induced drain leakage (GIDL) current in thin body devices: Single-gate ultra-thin body, symmetrical double-gate, and asymmetrical double-gate MOSFETs
Choi, Y.-K. (ykchoi@eecs.berkeley.edu), 1600, Japan Society of Applied Physics (42):
[4] Analysis of a novel elevated source drain MOSFET with-induced gate-induced drain-leakage current
Kim, KW
Choi, CS
Choi, WY
2000 IEEE HONG KONG ELECTRON DEVICES MEETING, PROCEEDINGS, 2000, : 36 - 39
[5] Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs
Sharma, Rajiv
Pandey, Sujata
Jain, Shail Bala
JOURNAL OF SEMICONDUCTORS, 2012, 33 (02)
[6] Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs
Rajiv Sharma
Sujata Pandey
Shail Bala Jain
半导体学报, 2012, 33 (02) : 28 - 35
[7] An analytical drain current model for symmetric double-gate MOSFETs
Yu, Fei
Huang, Gongyi
Lin, Wei
Xu, Chuanzhong
AIP ADVANCES, 2018, 8 (04):
[8] GATE-INDUCED DRAIN LEAKAGE CURRENT IN MOS DEVICES
NATHAN, V
DAS, NC
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (10) : 1888 - 1890
[9] Investigation and Optimization of Double-gate MPI 1T DRAM with Gate-induced Drain Leakage Operation
Ha, Jongmin
Lee, Jae Yoon
Kim, Myeongseon
Cho, Seongjae
Cho, Il Hwan
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2019, 19 (02) : 165 - 171
[10] Explicit model for the gate tunneling current in double-gate MOSFETs
Chaves, Ferney
Jimenez, David
Sune, Jordi
SOLID-STATE ELECTRONICS, 2012, 68 : 93 - 97

← 1 2 3 4 5 →