Exploring Hybrid Memory Caches in Chip Multiprocessors

被引：0

作者：

Donyanavard, Bryan ^{[1
]}

Monazzah, Amir Mandi Hosseini ^{[2
]}

Muck, Tiago ^{[1
]}

Dutt, Nikil ^{[1
]}

机构：

[1] Univ Calif Irvine, Irvine, CA 92717 USA

[2] Inst Res Fundamental Sci IPM, Sch Comp Sci, Tehran, Iran

来源：

PROCEEDINGS OF THE 2018 13TH INTERNATIONAL SYMPOSIUM ON RECONFIGURABLE COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC) | 2018年

关键词：

ARCHITECTURE; PERFORMANCE; ENERGY; MRAM;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Studies have shown memory needs vary significantly across applications. Recent work has explored using hybrid memory technology (SRAM+NVM) in on-chip memories of multi-core processors (CMPs) to support the varied needs of diverse workloads. Such works suggest architectural modifications that require supplemental management in the memory hierarchy. Instead, we propose to deploy hybrid memory in a manner that integrates seamlessly with the existing heterogeneous multicore (HMP) architectural model, and therefore does not require any supplemental management, simply the integration of different memory technologies on-chip. We evaluate platforms with a combination of fast (SRAM cache) and slow (STT-MRAM cache) core-types for mobile workloads.

引用

页数：8

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