Exploring Hybrid Memory Caches in Chip Multiprocessors

Studies have shown memory needs vary significantly across applications. Recent work has explored using hybrid memory technology (SRAM+NVM) in on-chip memories of multi-core processors (CMPs) to support the varied needs of diverse workloads. Such works suggest architectural modifications that require supplemental management in the memory hierarchy. Instead, we propose to deploy hybrid memory in a manner that integrates seamlessly with the existing heterogeneous multicore (HMP) architectural model, and therefore does not require any supplemental management, simply the integration of different memory technologies on-chip. We evaluate platforms with a combination of fast (SRAM cache) and slow (STT-MRAM cache) core-types for mobile workloads.