Mechanisms for enhancement of sensing performance in CMOS ISFET arrays using reactive ion etching

In this work, we investigate the impact of successively removing the passivation layers of ISFET sensors implemented in a standard CMOS process to improve sensing performance. Reactive ion etching is used as a post-processing technique of the CMOS chips for uniform and accurate etching. The removal of the passivation layers addresses common issues with commercial implementation of ISFET sensors, including pH sensitivity, capacitive attenuation, trapped charge, drift and noise. The process for removing the three standard layers (polyimide, Si3N4 and SiO2) is tailored to minimise the surface roughness of the sensing layer throughout an array of more than 4000 ISFET sensors. By careful calibration of the plasma recipe we perform material-wise etch steps at the top and middle of the nitride layer and top of the oxide layer. The characterisation of the ISFET array proves that the location of the trapped charge in the passivation layers is mainly at the interface of the layers. Etching to the top of the oxide layer is shown to induce an improvement of 80% in the offset range throughout the array and an increase in SNR of almost 40 dB compared to the non-processed configuration. The performance enhancement demonstrates the benefit of a controlled industry-standard etch process on CMOS ISFET array system-on-chips.