Nanoscale CMOSFET performance improvement and reliability study for local strain techniques

被引:6
作者
Huang, Hui Ling [1 ]
Chen, Jem-Kun [2 ]
Houng, Mau Phon [1 ]
机构
[1] Natl Cheng Kung Univ, Dept Elect Engn, Inst Microelect, Tainan 701, Taiwan
[2] Natl Taiwan Univ Sci & Technol, Dept Mat Engn, Taipei 106, Taiwan
关键词
Contact etch stop layer (CESL); Recess S/D SiGe; Nanoscale device; P-MOSFET; SILICON; SI;
D O I
10.1016/j.sse.2012.08.002
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we report the investigation on a nanoscale complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) fabricated by local strained channel techniques with epitaxial silicon-germanium (SiGe) and high mechanical stress SiN as contact etch stop layer (CESL). By integrating the SiGe layer with compressive stress and the SiN film with compressive and tensile strain, both PMOS and NMOS have better drain-to-source saturation current (Isat). For short channel effect, strain scheme also show beneficial results based on Vt-roll off performance. Furthermore when capping a strained tensile film, the interface trap density for NMOS could lower down 32% comparing to control Si from charge pumping current measurement which can indicate more stable initial gate oxide quality for NMOS. The impact of these stressor schemes on device reliability, such as negative bias temperature instability (NBTI) and hot carrier injection (HCI) have been studied to conclude that the hydrogen from compressive SiN is the key for reliability performance. (C) 2012 Elsevier Ltd. All rights reserved.
引用
收藏
页码:31 / 36
页数:6
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