Optimization of the Drive Circuit for Enhancement Mode Power GaN FETs in DC-DC Converters

被引：0

作者：

Xi, Youhao ^{[1
]}

Chen, Min ^{[1
]}

Nielson, Kim ^{[1
]}

Bell, Robert ^{[1
]}

机构：

[1] Texas Instruments Inc, Phoenix, AZ 85044 USA

来源：

2012 TWENTY-SEVENTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC) | 2012年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses the practical concerns and optimization of the drive circuit for enhancement mode Gallium-Nitride (GaN) power transistors in dc-dc converters. The GaN FET's 6.0V absolute maximum gate voltage rating and ultra low threshold voltage impose strict constrains on the drive circuit. It is critical to achieve precise gate voltage limit, realize a low impedance gate signal path, and meet the stringent noise immunity requirements by optimizing the gate drive circuit. Prototype converters were built and experimental results are presented as proof of concept.

引用

页码：2467 / 2471

页数：5

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