A 7 GHz Differential 4-Stage Programmable Equalizer with Hybrid Continuous-Time/Discrete-Time Architecture in 28 nm CMOS

被引：0

作者：

Morishita, Yohei ^{[1
]}

Sato, Junji ^{[1
]}

Takinami, Koji ^{[1
]}

Takahashi, Kazuaki ^{[1
]}

机构：

[1] Panasonic Corp, Engn Div, Automot & Ind Syst Co, Tsuzuki Ku, 600 Saedo Cho, Yokohama, Kanagawa 2248539, Japan

来源：

2018 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS (APMC) | 2018年

关键词：

Continuous time systems; Discrete time systems; Equalizer; CMOS; Analog integrated circuits; FILTER;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a programmable wideband equalizer with hybrid Continuous-Time (CT)/Discrete-Time (DT) architecture. Unlike the conventional hybrid CT/DT LPF, the proposed circuit enables large compensation level (CL) at high peaking frequencies. A prototype has been fabricated in 28 nm CMOS. The proposed equalizer achieves up to 7 GHz peaking frequency with more than 10dB of CL. In addition, it offers capacitance ratio (C ratio) and clock frequency (f(CK)) programmability. The proposed equalizer occupies 0.061 mm(2) of active area.

引用

页码：714 / 716

页数：3

共 5 条

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Morishita, Yohei
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Sato, Junji
Takinami, Koji
Takahashi, Kazuaki
[J]. IEICE TRANSACTIONS ON ELECTRONICS, 2017, E100C (10): : 858 - 865
[5] An equalized ultra-wideband channel-select filter with a discrete-time charge-domain band-pass IIR filter
Yoshizawa, Atsushi
Iida, Sachio
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