HIGH PERFORMANCE AND HIGHLY UNIFORM METAL HI-K GATE-ALL-AROUND SILICON NANOWIRE MOSFETS

被引:1
作者
Sleight, J. [1 ]
Bangsaruntip, S. [1 ]
Cohen, G. [1 ]
Majumdar, A. [1 ]
Zhang, Y. [1 ]
Engelmann, S. [1 ]
Fuller, N. [1 ]
Gignac, L. [1 ]
Mittal, S. [1 ]
Newbury, J. [1 ]
Barwicz, T. [1 ]
Frank, M. [1 ]
Guillorn, M. [1 ]
机构
[1] IBM TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA
来源
ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 6: NEW MATERIALS, PROCESSES, AND EQUIPMENT | 2010年 / 28卷 / 01期
关键词
D O I
10.1149/1.3375600
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I-DSAT = 825/950 mu A/mu m (circumference-normalized) or 2592/2985 mu A/mu m (diameter-normalized) at supply voltage V-DD = 1 V and off-current I-OFF = 15 nA/mu m. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.
引用
收藏
页码:179 / 189
页数:11
相关论文
共 11 条
  • [1] APPENZELLER J, 2006, IEDM, P555
  • [2] Cohen G.M., 2008, DRC TECH DIG, P187
  • [4] Hydrogen annealing of arrays of planar and vertically stacked Si nanowires
    Dornel, E.
    Ernst, T.
    Barbe, J. C.
    Hartmann, J. M.
    Delaye, V.
    Aussenac, F.
    Vizioz, C.
    Borel, S.
    Maffini-Alvaro, V.
    Isheden, C.
    Foucher, J.
    [J]. APPLIED PHYSICS LETTERS, 2007, 91 (23)
  • [5] STRESS IN THERMAL SIO2 DURING GROWTH
    EERNISSE, FP
    [J]. APPLIED PHYSICS LETTERS, 1979, 35 (01) : 8 - 10
  • [6] Gate Length and Performance Scaling of Undoped-Body Extremely Thin SOI MOSFETs
    Majumdar, Amlan
    Wang, Xinlin
    Kumar, Arvind
    Holt, Judson R.
    Dobuzinsky, David
    Venigalla, Raj
    Ouyang, Christine
    Koester, Steven J.
    Haensch, Wilfried
    [J]. IEEE ELECTRON DEVICE LETTERS, 2009, 30 (04) : 413 - 415
  • [7] NARASIMHA S, 2006, IEDM, P689
  • [8] Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs
    Oh, SH
    Monroe, D
    Hergenrother, JM
    [J]. IEEE ELECTRON DEVICE LETTERS, 2000, 21 (09) : 445 - 447
  • [9] FinFET design considerations based on 3-D simulation and analytical modeling
    Pei, G
    Kedzierski, J
    Oldiges, P
    Ieong, M
    Kan, ECC
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (08) : 1411 - 1419
  • [10] Numerical study on shape transformation of silicon trenches by high-temperature hydrogen annealing
    Sudoh, K
    Iwasaki, H
    Kuribayashi, H
    Hiruta, R
    Shimizu, R
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2004, 43 (9A): : 5937 - 5941