Bias Temperature Instability in High-κ/Metal Gate Transistors - Gate Stack Scaling Trends

With the introduction of High-k, metal gates and alternate substrates into the gate-stack at the 45nm and 32nm technology nodes, Bias Temperature Instability (BTI) phenomena have had to be included into the chip design modeling. In this paper, we explore BTI trends with High-k transistors in manufacturing ready CMOS processes with gate last and gate first type process flows. In both flows, Positive Bias Temperature Instability (PBTI) is a strong function of the interface and High-k thickness, with aggressive interface scaling having significant adverse reliability implications. Negative Bias Temperature Instability, on the other hand, is strongly dependent on the quality of the interface and its nitrogen content. The introduction of germanium into the Si channel is found to significantly improve NBTI. With recovery effects being strong in both NBTI and PBTI, AC BTI models in realistic circuit designs are critical to accurately evaluate the BTI lifetime of chips.