A Compact Model for Single Event Effects in PD SOI Sub-Micron MOSFETs

This paper presents a compact model implemented in Verilog-A for partially depleted (PD) silicon-on-insulator (SOI) sub-micron MOSFETs, which allows for describing the Single Events Effects (SEE) produced by heavy ions. This Verilog-A module can be coupled with Spice simulator in order to have faster (time-efficient) circuit simulations with good agreement. Due to the physical aspects considered in the model, better flexibility than the standard current source method is achieved. Experimental data for 0.15 and 0.13 mu m technology nodes are used to validate our model. Robustness of the model to reproduce experimental results is demonstrated on three data-sets available in literature: 1) single event transient current in stand-alone n-FET from 0.13 mu m PD SOI process hinted by heavy ions at different positions; 2) SEE propagation in path delay with ten inverters realized in 0.13 mu m PD SOI process; 3) 6T SRAMs with active element delay on SEE-rad-hardened 0.15 mu m PD SOI process.