Neuro-Inspired Computing With Emerging Nonvolatile Memory

被引:839
作者
Yu, Shimeng [1 ]
机构
[1] Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85287 USA
关键词
Hardware accelerator; machine learning; neuromorphic computing; neural network; nonvolatile memory; resistive memory; synaptic device; RANDOM-ACCESS MEMORY; MEMRISTOR; SYNAPSES; NETWORK; DEVICE; PLASTICITY; STORAGE; SYSTEM; ENGINE; ARRAY;
D O I
10.1109/JPROC.2018.2790840
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This comprehensive review summarizes state of the art, challenges, and prospects of the neuro-inspired computing with emerging nonvolatile memory devices. First, we discuss the demand for developing neuro-inspired architecture beyond today's von-Neumann architecture. Second, we summarize the various approaches to designing the neuromorphic hardware (digital versus analog, spiking versus nonspiking, online training versus offline training) and discuss why emerging nonvolatile memory is attractive for implementing the synapses in the neural network. Then, we discuss the desired device characteristics of the synaptic devices (e.g., multilevel states, weight update nonlinearity/asymmetry, variation/noise), and survey a few representative material systems and device prototypes reported in the literature that show the analog conductance tuning. These candidates include phase change memory, resistive memory, ferroelectric memory, floating-gate transistors, etc.Next, we introduce the crossbar array architecture to accelerate the weighted sum and weight update operations that are commonly used in the neuro-inspired machine learning algorithms, and review the recent progresses of array-level experimental demonstrations for pattern recognition tasks. In addition, we discuss the peripheral neuron circuit design issues and present a device-circuit-algorithm codesign methodology to evaluate the impact of nonideal device effects on the system-level performance (e.g., learning accuracy). Finally, we give an outlook on the customization of the learning algorithms for efficient hardware implementation.
引用
收藏
页码:260 / 285
页数:26
相关论文
共 130 条
[41]  
Bayat FM, 2015, IEEE INT SYMP CIRC S, P1921, DOI 10.1109/ISCAS.2015.7169048
[42]   Visual Pattern Extraction Using Energy-Efficient "2-PCM Synapse" Neuromorphic Architecture [J].
Bichler, Olivier ;
Suri, Manan ;
Querlioz, Damien ;
Vuillaume, Dominique ;
DeSalvo, Barbara ;
Gamrat, Christian .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (08) :2206-2214
[43]   Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element [J].
Burr, Geoffrey W. ;
Shelby, Robert M. ;
Sidler, Severin ;
di Nolfo, Carmelo ;
Jang, Junwoo ;
Boybat, Irem ;
Shenoy, Rohit S. ;
Narayanan, Pritish ;
Virwani, Kumar ;
Giacometti, Emanuele U. ;
Kuerdi, Bulent N. ;
Hwang, Hyunsang .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (11) :3498-3507
[44]   A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit [J].
Chakrabarti, B. ;
Lastras-Montano, M. A. ;
Adam, G. ;
Prezioso, M. ;
Hoskins, B. ;
Cheng, K. -T. ;
Strukov, D. B. .
SCIENTIFIC REPORTS, 2017, 7
[45]   Short-Term Memory to Long-Term Memory Transition in a Nanoscale Memristor [J].
Chang, Ting ;
Jo, Sung-Hyun ;
Lu, Wei .
ACS NANO, 2011, 5 (09) :7669-7676
[46]  
Chen PY, 2015, ICCAD-IEEE ACM INT, P194, DOI 10.1109/ICCAD.2015.7372570
[47]  
Chen PY, 2015, DES AUT TEST EUROPE, P854
[48]  
Chen P, 2016, I C MECH MACH VIS PR, P1
[49]  
Chen YH, 2016, ISSCC DIG TECH PAP I, V59, P262, DOI 10.1109/ISSCC.2016.7418007
[50]  
Courbariaux M, 2015, ADV NEUR IN, V28