Optimization Techniques for CNT Based VLSI Interconnects - A Review

被引:20
作者
Karthikeyan, A. [1 ]
Mallick, P. S. [1 ]
机构
[1] VIT Univ, Sch Elect Engn, Vellore 632014, Tamil Nadu, India
关键词
Interconnect; buffer; repeater insertion; delay; crosstalk; VLSI; OPTIMAL REPEATER INSERTION; CARBON-NANOTUBE; BUFFER INSERTION; PERFORMANCE EVALUATION; GLOBAL INTERCONNECTS; DELAY; POWER; BUNDLE; DESIGN; METHODOLOGY;
D O I
10.1142/S0218126617300021
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22 nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.
引用
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页数:15
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