Low Complexity and Low Power Multiplierless FIR Filter Implementation

被引：0
|
作者：
Lou, Xin [1 ]
Ye, Wenbin [2 ]
机构：
[1] ShanghaiTech Univ, Sch Informat Sci & Technol, Shanghai, Peoples R China
[2] Shenzhen Univ, Sch Elect Sci & Technol, Shenzhen, Peoples R China
来源：
2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2017年
关键词：
DIGITAL-FILTERS; MULTIPLE;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
For the implementation of multiplierless FIR filters, the product accumulation block (PAB) in the transposed direct form (TDF) structure has been ignored for a long time. In this work, the hardware complexity and power consumption of the PAB is investigated. It is shown that the PAB contributes the majority of hardware complexity and power consumption in multiplierless FIR filter circuits. Implementation methods for the PAB are proposed to reduce the overall hardware complexity or power consumption of multiplierless FIR filters. Experimental results show that the overall hardware complexity and power consumption can be reduced significantly.
引用
收藏
页码：596 / 599
页数：4
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