Performance prediction tools for parallel discrete-event simulation

被引:3
作者
Lim, CC [1 ]
Low, YH [1 ]
Gan, BP [1 ]
Jain, S [1 ]
Cai, WT [1 ]
Hsu, WJ [1 ]
Huang, SY [1 ]
机构
[1] Gint Inst Mfg Technol, Singapore 638075, Singapore
来源
THIRTEENTH WORKSHOP ON PARALLEL AND DISTRIBUTED SIMULATION - PROCEEDINGS | 1999年
关键词
D O I
10.1109/PADS.1999.766171
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
We have developed a set of performance prediction teals which help to estimate the achievable speedups from parallelizing a sequential simulation. The tools focus on two important factors in the actual speedup of a parallel simulation program : (a) the simulation protocol used, and (b) the inherent parallelism in the simulation model. The first two tools are a performance/parallelism analyzer for a conservative, asynchronous simulation protocol and a similar analyzer for a conservative, synchronous ("super-step") protocol. Each analyzer allows us to study how the speedup of a model changes with increasing number of processors, when a specific protocol is used. The third tool - a critical path analyzer - gives an ideal upper bound to the model's speedup. This paper gives an overview of the prediction tools, and reports the predictions from applying the tools to a discrete-event wafer fabrication simulation model. The predictions are close to speedups from actual parallel implementations. These tools help us to set realistic expectations of the speedup from a parallel simulation program, and to focus our work on issues which are more likely to yield performance improvement.
引用
收藏
页码:148 / 155
页数:8
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