Evaluating Selective Redundancy in Data-Flow Software-Based Techniques

被引：13

作者：

Chielle, Eduardo ^{[1
,2
]}

Azambuja, Jose Rodrigo ^{[1
,2
]}

Barth, Raul Serio ^{[1
,2
]}

Almeida, Felipe ^{[1
,2
]}

Kastensmidt, Fernanda Lima ^{[1
,2
]}

机构：

[1] Univ Fed Rio Grande do Sul, Inst Informat, PPGC, BR-91509900 Porto Alegre, RS, Brazil

[2] Univ Fed Rio Grande do Sul, PGMICRO, BR-91509900 Porto Alegre, RS, Brazil

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2013年 / 60卷 / 04期

关键词：

Fault tolerance; microprocessors; selective redundancy; soft errors; software-based techniques; CO-DESIGN APPROACH; MITIGATION;

D O I：

10.1109/TNS.2013.2266917

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an analysis of the efficiency of using selective redundancy applied to registers in software-based techniques. The proposed selective redundancy chooses a set of allocated registers to be duplicated in software in order to provide detection of upsets that occur in the processor hardware and provokes data-flow errors. The selective redundancy is implemented over miniMIPS microprocessor software. A fault injection campaign is performed by injecting single event effect upsets in the miniMIPS hardware. Results show error detection capability, performance degradation and program memory footprint for many case studies. With that, designers can find the best trade-off in using selective redundancy in software.

引用

页码：2768 / 2775

页数：8

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