Compact current-mode loop filter for PLL applications

A novel capacitance scaling technique is proposed to reduce on-chip capacitor area using a dual-path self-biased current-mode filter. The capacitor multiplier is obtained by the relative ratio of charge-pump currents I-cp2/(I-cp2-I-cp1), rather than the scaling ratio I-cp2/I-cp1. Compared with the original current-mode filter, the demonstrated loop filter of 250 pF capacitance is achieved with only 25 pF (90% die area saving), and the resistor area is reduced by 50% owing to reuse of the degenerated resistor RG.