Compact current-mode loop filter for PLL applications

被引：4
作者：
Yan, J [1 ]
Zheng, H
Zeng, X
Tang, T
机构：
[1] Fudan Univ, ASIC, Shanghai 200433, Peoples R China
[2] Fudan Univ, Syst State Key Lab, Shanghai 200433, Peoples R China
来源：
ELECTRONICS LETTERS | 2005年 / 41卷 / 23期
关键词：
D O I：
10.1049/el:20052781
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel capacitance scaling technique is proposed to reduce on-chip capacitor area using a dual-path self-biased current-mode filter. The capacitor multiplier is obtained by the relative ratio of charge-pump currents I-cp2/(I-cp2-I-cp1), rather than the scaling ratio I-cp2/I-cp1. Compared with the original current-mode filter, the demonstrated loop filter of 250 pF capacitance is achieved with only 25 pF (90% die area saving), and the resistor area is reduced by 50% owing to reuse of the degenerated resistor RG.
引用
收藏
页码：1257 / 1258
页数：2
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