Low-Vt TaN/HfLaO n-MOSFETs Using Low-Temperature Formed Source-Drain Junctions

被引:5
作者
Lin, S. H. [1 ]
Liu, S. L. [2 ]
Yeh, F. S. [1 ]
Chin, Albert [2 ,3 ]
机构
[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 30013, Taiwan
[2] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
[3] Nanoelect Consortium Taiwan, Hsinchu 300, Taiwan
关键词
HfLaO; low V-t; solid-phase diffusion (SPD); SILICIDE; CMOS;
D O I
10.1109/LED.2008.2009011
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We report low-threshold-voltage (V-t) TaN/HfLaO n-MOSFETs using solid-phase-diffusion (SPD)-formed junctions at a low temperature of 650 degrees C. The gate-first and self-aligned TaN/HflLaO n-MOSFETs using Ni/Sb SPID-formed source-drain junctions showed a low Vt of 0.16 V and a peak electron mobility of 187 cm(2)/V . s at a small 1.3-nm equivalent oxide thickness.
引用
收藏
页码:75 / 77
页数:3
相关论文
共 17 条
[1]   Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions [J].
Cheng, C. F. ;
Wu, C. H. ;
Su, N. C. ;
Wang, S. J. ;
McAlister, S. P. ;
Chin, Albert .
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :333-+
[2]  
HSU PF, 2006, VLSI S, P11
[3]  
Huang CH, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P319
[4]  
Kinoshita A, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P168
[5]   Careful examination on the asymmetric Vfb shift problem for poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expense [J].
Koyama, M ;
Kamimuta, Y ;
Ino, T ;
Kaneko, A ;
Inumiya, S ;
Eguchi, K ;
Takayanagi, M ;
Nishiyama, A .
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :499-502
[6]   Formation of Ni germano-silicide on single crystalline Si0.3Ge0.7/Si [J].
Lin, CY ;
Chen, WJ ;
Lai, CH ;
Chin, A ;
Liu, J .
IEEE ELECTRON DEVICE LETTERS, 2002, 23 (08) :464-466
[7]  
Maszara WP, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P367, DOI 10.1109/IEDM.2002.1175854
[8]   Thermally stable fully silicided Hf-silicide metal-gate electrode [J].
Park, CS ;
Cho, BJ ;
Kwong, DL .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (06) :372-374
[9]   Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices [J].
Takahashi, K ;
Manabe, K ;
Ikarashi, T ;
Ikarashi, N ;
Hase, T ;
Yoshihara, T ;
Watanabe, H ;
Tatsumi, T ;
Mochizuki, Y .
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :91-94
[10]  
TAVEL B, 2001, IEDM, P815