Design of Low Power and Improved tlatch Comparator for SAR ADC

被引：0

作者：

Sharuddin, Iffa ^{[1
]}

Lee, L. ^{[1
]}

机构：

[1] Multimedia Univ, Fac Engn, Cyberjaya 63100, Selangor, Malaysia

来源：

2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) | 2014年

关键词：

Dynamic Comparator; Analog-to-digital converter; Successive approximation;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The design of low power and improved t(latch) dynamic comparator for successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve low power performance, a modified dynamic comparator is proposed that use modified latch, utilizing NMOS transistor in the design. The t(latch) of the proposed comparator improved by approximately 45% compared to conventional comparator. The proposed dynamic comparator is designed and simulated in a 0.18 mu m CMOS process. Simulation results show that it only consumed 138 pW at 1.5 V power supply with clock frequency of 200 MHz.

引用

页码：631 / 634

页数：4

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