A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations

被引：0
作者：
Hsiao, SF
机构：
来源：
ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI | 1999年
关键词：
CORDIC; signed-digit representation; redundant arithmetic; VLSI;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new high-speed redundant CORDIC processor with constant scaling factor is designed. Compared to previously proposed redundant CORDIC methods, the new processor not only preserves the constancy of the scaling factor, but also performs the scaling operation within the regular iterations Thus, the processor does not require any complicated division/square-rooting operations, extra correcting iterations, or additional scaling iterations. VLSI implementation result of the new redundant CORDIC processor is also included.
引用
收藏
页码：455 / 458
页数：4
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