High-performance and low-power bulk logic platform utilizing FET specific multiple-stressors with highly enhanced strain and full-porous low-k interconnects for 45-nm CMOS technology

被引：28

作者：

Miyashita, T. ^{[1
]}

Ikeda, K. ^{[1
]}

Kim, Y. S. ^{[1
]}

Yamamoto, T. ^{[1
,2
]}

Sambonsugi, Y. ^{[1
]}

Ochimizu, H. ^{[1
]}

Sakoda, T. ^{[1
]}

Okuno, M. ^{[1
]}

Minakata, H. ^{[1
]}

Ohta, H. ^{[1
]}

Hayami, Y. ^{[1
]}

Ookoshi, K. ^{[2
]}

Shimamune, Y. ^{[1
]}

Fukuda, M. ^{[2
]}

Hatada, A. ^{[2
]}

Okabe, K. ^{[2
]}

Kubo, T. ^{[2
]}

Tajima, M. ^{[2
]}

Yamamoto, T. ^{[1
,2
]}

Motoh, E. ^{[2
]}

Owada, T. ^{[2
]}

Nakamura, M. ^{[1
]}

Kudo, R. ^{[1
]}

Sawada, T. ^{[2
]}

Nagayama, J. ^{[2
]}

Satoh, A. ^{[1
]}

Mori, T. ^{[2
]}

Hasegawa, A. ^{[2
]}

Kurata, H. ^{[1
]}

Sukegawa, K. ^{[1
]}

Tsukune, A. ^{[1
]}

Yamaguchi, S. ^{[2
]}

Ikeda, K. ^{[1
]}

Kase, M. ^{[2
]}

Futatsugi, T. ^{[1
]}

Satoh, S. ^{[1
]}

Sugii, T. ^{[1
]}

机构：

[1] Fujitsu Labs Ltd, 50 Fuchigami, Tokyo 1970833, Japan

[2] Fujitsu Ltd, Tokyo 1970833, Japan

来源：

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/IEDM.2007.4418915

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mu m at 100 nA/ mu m off-current, and 0.97/0.63 mA/mu m at 10 nA/mu m off-current at vertical bar V-d vertical bar = 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mu m(2). In addition, full-porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

引用

页码：251 / +

页数：3

共 7 条

[1] Strategies of RC delay reduction in 45 nm BEOL technology [J].

Kudo, H. ;

Ochimizu, H. ;

Tsukune, A. ;

Okano, S. ;

Naitou, K. ;

Sakamoto, M. ;

Takesako, S. ;

Shirasu, T. ;

Asneil, A. ;

Idani, N. ;

Sugimoto, K. ;

Ozaki, S. ;

Nakata, Y. ;

Owada, T. ;

Watatani, H. ;

Ohara, N. ;

Ohtsuka, N. ;

Sunayama, M. ;

Sakai, H. ;

Oryoji, M. ;

Akiyama, S. ;

Iwata, H. ;

Yamamoto, H. ;

Shimoda, Y. ;

Yao, T. ;

Suda, S. ;

Suzuki, T. ;

Sakai, S. ;

Kitada, H. ;

Amari, S. ;

Tabira, T. ;

Matsuura, A. ;

Iba, Y. ;

Mizushima, Y. ;

Matsuyama, H. ;

Suzuki, Y. ;

Shimizu, N. ;

Yanai, K. ;

Nakaishi, M. ;

Futatsugi, T. ;

Hanyu, I. ;

Nakamura, T. ;

Sugii, T. .

PROCEEDINGS OF THE IEEE 2007 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2007, :178-+

[2] High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology [J].

Luo, Z. ;

Rovedo, N. ;

Ong, S. ;

Phoong, B. ;

Eller, M. ;

Utomo, H. ;

Ryou, C. ;

Wang, H. ;

Stierstorfer, R. ;

Clevenger, L. ;

Kim, S. ;

Toomey, J. ;

Sciacca, D. ;

Li, J. ;

Wille, W. ;

Zhaol, L. ;

Teo, L. ;

Dyer, T. ;

Fang, S. ;

Yan, J. ;

Kwon, O. ;

Park, D. ;

Holt, J. ;

Han, J. ;

Chan, V. ;

Yuan, J. ;

Kebede, T. ;

Lee, H. ;

Kim, S. ;

Lee, S. ;

Vayshenker, A. ;

Yang, Z. ;

Tian, C. ;

Ng, H. ;

Shang, H. ;

Hierlemann, M. ;

Ku, J. ;

Sudijonol, J. ;

Ieong, M. .

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, :16-+

[3]

NII H, 2006, IEDM, P685

[4] Novel thin sidewall structure for high performance bulk CMOS with charge-assisted source-gain-extension [J].

Ohta, H. ;

Fukutome, H. ;

Sakuma, T. ;

Hatada, A. ;

Ohkoshi, K. ;

Ikeda, K. ;

Miyashita, T. ;

Mori, T. ;

Sugii, T. .

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, :120-+

[5]

Ohta H, 2005, INT EL DEVICES MEET, P247

[6] Multiple stress memorization in advanced SOICMOS technologies [J].

Wei, A. ;

Wiatr, M. ;

Mowry, A. ;

Gehring, A. ;

Boschke, R. ;

Scott, C. ;

Hoentschel, J. ;

Duenkel, S. ;

Gerhardt, M. ;

Feudel, T. ;

Lenski, M. ;

Wirbeleit, F. ;

Otterbach, R. ;

Callahan, R. ;

Koerner, G. ;

Krumm, N. ;

Greenlaw, D. ;

Raab, M. ;

Horstmann, M. .

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, :216-+

[7] Advantages of a new scheme of junction profile engineering with laser spike annealing and its integration into a 45-nm node high performance CMOS technology [J].

Yamamoto, T. ;

Kubo, T. ;

Sukegawa, T. ;

Katakami, A. ;

Shimamune, Y. ;

Tamura, N. ;

Ohta, H. ;

Miyashita, T. ;

Sato, S. ;

Kase, M. ;

Sugii, T. .

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, :122-+

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