A Ultra High Speed and Configurable Inverse Discrete Wavelet Packet Transform Architecture

This article presents a new pipeline-parallel architecture of Inverse Discrete Wavelet Packet Transform (IDWPT) for all wavelet family implemented in FPGA technology using a parallel direct FIR filter. Our aim in this work is to develop a generic VHDL-RTL model and configurable architecture of pipeline-parallel architecture of IDWPT. This architecture provide ultra-high speed sample processing with a restricted amount of used hardware. To achieve that, we propose a P-parallel IDWPT based on Mallat binary tree algorithm and a P-parallel/modified direct FIR filter under the strategy of pipeline parallel and sharing hardware resource. The key of this model is the data manage/interleaving of pipeline/P-parallel concept and shared hardware of different level in the transformation. This architecture is fully configurable: (i) in synthesis according of various parameters like the parallel degree, the tree depth (number of tree levels), the order of the filters and the filter quantization coefficient and (ii) in pro-synthesis according to the coefficients of low-pass and high-pass filters, in other words the filters coefficients can be loaded after synthesis. Consequently, the simulation results accelerated to an approximate value of P*(Frequency). Furthermore, the tree depth and filters order has little impact (only due to place and route variations) on throughput. This architecture was synthesized using Altera Quartus prime lite edition targeting an Altera Cyclone IV - (FPGA) and it was developed in VHDL at RTL level modeling.