Investigation of the Power-Clock Network Impact on Adiabatic Logic

被引：0

作者：

Jeanniot, Nicolas ^{[1
]}

Todri-Sanial, Aida ^{[1
]}

Nouet, Pascal ^{[1
]}

Pillonnet, Gael ^{[2
]}

Fanet, Herve ^{[2
]}

机构：

[1] Univ Montpellier, CNRS, LIRMM, Montpellier, France

[2] CEA, LETI, MINATEC, DACLE, Grenoble, France

来源：

2016 IEEE 20TH WORKSHOP ON SIGNAL AND POWER INTEGRITY (SPI) | 2016年

关键词：

Adiabatic Logic; Power-Clock Distribution Network; Power Efficiency;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Adiabatic logic is architecture design style which seems to be a good candidate to reduce the power consumption of digital cores. One key difference is that the power supply is also the clock signal. A lot of work on different adiabatic logic families has been done but the impact of the power supply and the power-clock network still remains to be studied. In this paper, we investigate the power-clock network effect on adiabatic energy dissipation. We derive closed-form analytical formulas to represent the output signal voltage and energy dissipation while taking into account the parasitic impedance of the power-clock network with respect to switching frequency such that adiabatic conditions are still met. Experiments, based on simulation, show that the power-clock network impacts both the energy efficiency of the circuit and its frequency.

引用

页数：4

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