A low-power/low-noise readout circuit for integrated capacitive sensors

被引：20

作者：

Dimitropoulos, Panagiotis D. ^{[1
]}

Karampatzakis, Dimitris P.

Panagopoulos, Georgios D.

Stamoulis, Georgios I.

机构：

[1] Swiss Fed Inst Technol, Inst Microelect & Microsyst, CH-1014 Lausanne, Switzerland

[2] Univ Thessaly, Dept Comp & Telecommun Engn, Volos 38221, Greece

来源：

IEEE SENSORS JOURNAL | 2006年 / 6卷 / 03期

关键词：

ASIC; capacitive sensor; CMOS analog IC; low power; switched capacitor;

D O I：

10.1109/JSEN.2006.874439

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A switched-capacitor integrated system is presented in this work that attains sub-fF measurement resolution in integrated capacitive sensors, with 1.5-kHz bandwidth and 50-mu W average power consumption in continuous function mode. The proposed design employs a pair of nonoverlapping clocks and an operational transconductance amplifier (OTA) that can be made as simple as a basic differential pair. The system exhibits 0.8% linearity error and 0.01 fF/degrees C temperature drift. It is appropriate for differential, absolute, and ratiometric capacitance measurements, and shows robustness against interconnection parasitics, transistor dimensional mismatch, and process variations, which are an important feature in the case of sensor-die CMOS postprocessing.

引用

页码：755 / 769

页数：15

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