A Robust Receiver for Power Line Communications in Integrated Circuits

被引：0

作者：

Salem, Jebreel ^{[1
]}

Ha, Dong Sam ^{[1
]}

机构：

[1] Virginia Tech, Bradley Dept Elect & Comp Engn, Ctr Embedded Syst Crit Applicat CESCA, Blacksburg, VA 24061 USA

来源：

2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2012年

关键词：

Power line communications; PLC; PLC Receiver; Power Pins; Voltage Variation; DUAL-USE;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a power line communications (PLC) receiver in ICs with emphasis on robustness. The PLC receiver intends to control internal logic values of ICs through power pins. It employs a differential Schmitt trigger to increase noise immunity and tolerate supply voltage fluctuations. The receiver is designed and laid out in 0.18 mu m CMOS technology. Post-layout simulation results show that the receiver can operate up to 22.2 percent of the supply voltage drop under the signal-to-noise ratio (SNR) of 16.3 dB. The receiver dissipates 2.4 mW under 1.8 V supply, which is lower than earlier PLC receivers.

引用

页码：254 / 257

页数：4

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