Configurable 3D-integrated focal-plane cellular sensor-processor array architecture

被引：19
作者：
Foldesy, Peter [1 ,2 ]
Zarandy, Akos [1 ,2 ]
Rekeczky, Csaba [1 ,2 ]
机构：
[1] Hungarian Acad Sci, Comp & Automat Res Inst, Cellular Sensory & Wave Comp Res Lab, H-1111 Budapest, Hungary
[2] Eutecus Inc, Berkeley, CA USA
来源：
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | 2008年 / 36卷 / 5-6期
关键词：
focal plane; sensor-processor; parallel processing; SIMD; 3D integration;
D O I：
10.1002/cta.509
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Mixed-signal cellular visual microprocessor architecture with digital processors is described. An Application Specific Integrated Circuit (ASIC) implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face-to-face-type integration, and one or several cascaded array of mainly identical (single instruction multiple data, SIMD) processing elements. The individual array elements were derived from the same general Hardware Description Language (HDL) description and could be of different sizes, aspect ratio, and computing resources. Copyright (c) 2008 John Wiley & Sons, Ltd.
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收藏
页码：573 / 588
页数：16
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