Physical design of dual-core system-on-chip

被引：20

作者：

Teng, ZW ^{[1
]}

Liu, P ^{[1
]}

Lai, LY ^{[1
]}

机构：

[1] Zhejiang Univ, Dept Informat Sci & Elect Engn, Hangzhou 310027, Peoples R China

来源：

PROCEEDINGS OF 2005 IEEE INTERNATIONAL WORKSHOP ON VLSI DESIGN AND VIDEO TECHNOLOGY | 2005年

关键词：

D O I：

10.1109/IWVDVT.2005.1504458

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

To meet the aggressive time-to-market requirement, fast prototyping methodology is employed to shorten design cycle. To satisfy stringent path timing, a novel diagonal floorplan is integrated to enhance the data sharing between different cores in system on chip. In this paper, physical design of MediaSOC3221A shows how system on chip is planed and unified, with balanced clock trees and effective power distribution. As a result, the physical design of a dual-core chip is accomplished in only five days with good performance*.

引用

页码：36 / 39

页数：4

共 10 条

[1]

AURANGZEB K, 2004, INT C INT CIRC DES T, P151

[2]

CHOI B, 2004, P 2004 INT S ISCAS M, V5, pV73

[3]

Dai WJ, 2003, ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, P635

[4] A physical design methodology for 1.3GHz SPARC64 microprocessor [J].

Ito, N ;

Komatsu, H ;

Tanamura, Y ;

Yamashita, R ;

Sugiyama, H ;

Sugiyama, Y ;

Hamamura, H .

21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, :204-210

[5] IBM power5 chip: A dual-core multithreaded processor [J].

Kalla, R ;

Sinharoy, B ;

Tendler, JM .

IEEE MICRO, 2004, 24 (02) :40-47

[6]

Lo JYL, 2003, DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, P1102

[7]

Mehrotra A, 2003, ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, P640, DOI 10.1109/ASPDAC.2003.1195102

[8] An explicit RC-circuit delay approximation based on the first three moments of the impulse response [J].

Tutuianu, B ;

Dartu, F ;

Pileggi, L .

33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996, 1996, :611-616

[9] The circuit andphysical design of the POWER4 microprocessor [J].

Warnock, JD ;

Keaty, JM ;

Petrovick, J ;

Clabes, JG ;

Kircher, CJ ;

Krauter, BL ;

Restle, PJ ;

Zoric, BA ;

Anderson, CJ .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2002, 46 (01) :27-51

[10]

ZHU QK, 2001, 8 IEEE INT C EL CIRC, V1, P417

← 1 →