Minimum Effort Design Space Subsetting for Configurable Caches

被引:3
作者
Alsafrjalani, Mohamad Hammam [1 ]
Gordon-Ross, Ann [1 ,3 ]
Viana, Pablo [2 ]
机构
[1] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
[2] Univ Fed Alagoas, FEAC Dept, Maceio, AL, Brazil
[3] NSF Ctr High Performance Reconfigurable Comp CHRE, Catharines, ON, Canada
来源
2014 12TH IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND UBIQUITOUS COMPUTING (EUC 2014) | 2014年
关键词
Design space exploration; configurable caches; cache tuning; design space subsetting;
D O I
10.1109/EUC.2014.19
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Configurable caches can significantly reduce energy consumption by adapting the system's cache configuration to the applications' specific requirements to meet system design and optimization goals. However, large configuration design spaces require prohibitive design space exploration time (e.g., due to lengthy design space analyses, simulations, and/or evaluations) to determine the best configuration given these requirements and goals. To significantly reduce design space exploration time, we evaluate a design space subsetting method that removes energy-redundant configurations (i.e., configurations that provide similar energy savings as other configurations), thus significantly reducing the design space while still providing high-quality, energy-saving configurations. Prior work verified design space subsetting's efficacy, however, prior work required extensive design-time effort and complete a priori knowledge of the system's anticipated applications. In this work, we alleviate these limitations and significantly broaden the usability of design space subsetting. Results show that complete a priori knowledge of the anticipated applications is not necessary, and only a small set of applications representative of the anticipated applications' general domains (or applications with similar requirements) is sufficient to provide energy savings within 5.6% of the complete, unsubsetted design space.
引用
收藏
页码:65 / 72
页数:8
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