An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing

被引:35
作者
Jendernalik, W. [1 ]
Blakiewicz, G. [1 ]
Jakusz, J. [1 ]
Szczepanski, S. [1 ]
Piotrowski, R. [1 ]
机构
[1] Gdansk Univ Technol, Fac Elect Telecommun & Informat, PL-80233 Gdansk, Poland
关键词
Analog processor array; CMOS vision sensor; low power image processing; vision chip; FPS;
D O I
10.1109/TCSI.2012.2215803
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3 x 3 kernel. The proof-of-concept circuit is implemented in 0.35 mu m CMOS technology, and contains a 64 x 64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 mu W per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s.
引用
收藏
页码:279 / 289
页数:11
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