Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

被引：117

作者：

Lee, Jri ^{[1
,2
]}

Chiang, Ping-Chuan ^{[1
]}

Peng, Pen-Jui ^{[1
]}

Chen, Li-Yang ^{[1
]}

Weng, Chih-Chi ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10764, Taiwan

[2] Atilia Technol, Taipei, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2015年 / 50卷 / 09期

关键词：

Clock and data recovery (CDR); equalizer; highspeed serial link; NRZ; PAM4; phase-locked loop (PLL); SerDes; transceiver (TRX); CLOCK RECOVERY;

D O I：

10.1109/JSSC.2015.2433269

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents two ultra-high-speed SerDes dedicated for PAM4 and NRZ data. The PAM4 TX incorporates an output driver with 3-tap FFE and adjustable weighting to deliver clean outputs at 4 levels, and the PAM4 RX employs a purely linear full-rate CDR and CTLE/1-tap DFE combination to recover and demultiplex the data. NRZ TX includes a tree-structure MUX with built-in PLL and phase aligner. NRZ RX adopts linear PD with special vernier technique to handle the 56 Gb/s input data. All chips have been verified in silicon with reasonable performance, providing prospective design examples for next-generation 400 GbE.

引用

页码：2061 / 2073

页数：13

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