A 35.56GHz All-Digital Phase-Locked Loop with High Resolution Varactors

被引：0

作者：

Hung, Chao-Ching ^{[1
]}

Liu, Shen-Iuan ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

来源：

2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT) | 2010年

关键词：

all-digital; phase-locked loop; high frequency resolution; varactor; CONTROLLED OSCILLATOR; FREQUENCY RESOLUTION;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 35.56GHz all-digital phase-locked loop with high resolution varactors is presented. To enhance the frequency resolution for a high-frequency digitally controlled oscillator, the proposed varactor with its body connected to digital control bits is presented. A 35.56GHz all-digital PLL is realized in 90nm CMOS process. The measured peak-to-peak jitter and rms jitter are 3.84ps and 349.1fs, respectively, at 35.56GHz.

引用

页码：245 / 248

页数：4

共 9 条

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