A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems

被引:2
作者
Lai, Bo-Cheng Charles [1 ]
Chen, Kuan-Ting [2 ]
Wu, Ping-Ru [3 ]
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30010, Taiwan
[2] Global Unichip Corp, Hsinchu 30076, Taiwan
[3] MediaTek Inc, Hsinchu 30076, Taiwan
关键词
Cache memory; multicore processing; simulation; system analysis and design; POWER;
D O I
10.1109/TVLSI.2014.2370761
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The snoopy-based protocol is a widely used cache coherence mechanism for a symmetric multiprocessor (SMP) system. However, this broadcast-based protocol blindly disseminates data sharing information across the system, and introduces many unnecessary data operations. This paper proposes a novel architecture of double-layer counting Bloom filter (DLCBF) to reduce the unnecessary data lookups on the local cache and redundant data transactions on the shared interconnection of an SMP system. By adding an extra filtering layer, the DLCBF effectively exploits the data locality of applications. The two-layer hierarchy reduces the storage size of DLCBF by 18.75%, and achieves 81.99% and 31.36% better filtering rates when compared with a classic Bloom filter (BF) and original counting BF, respectively. When applied on the segmented shared bus of an SMP system, the DLCBF outperforms the previous work by 58% for In-filters and 1.86x for Out-filters. This paper also comprehensively explores the key design parameters of DLCBF, including the sizes of top-layer, bottom-layer, and multilayer design. The results show that enlarging the layer filters enhance the filtering rates of DLCBF, while adding an extra filter layer only provides slight benefit.
引用
收藏
页码:2473 / 2486
页数:14
相关论文
共 30 条
[1]  
Ahmad M., 2008, IEEE Global Telecommunications Conference, P1
[2]   Scalable Bloom Filters [J].
Almeida, Paulo Sergio ;
Baquero, Carlos ;
Preguica, Nuno ;
Hutchison, David .
INFORMATION PROCESSING LETTERS, 2007, 101 (06) :255-261
[3]  
[Anonymous], INTR AMBA 4 ACE
[4]  
[Anonymous], 2011, BENCHMARKING MODERN
[5]  
[Anonymous], ARM926EJ S PERF POW
[6]  
[Anonymous], 2008, HPL200820
[7]  
[Anonymous], CORELINK TM CCI 400
[8]  
Bienia C., 2010, Proceedings of the IEEE International Symposium on Workload Characterization (IISWC'10), IISWC '10, P1
[9]  
Binkert Nathan, 2011, Computer Architecture News, V39, P1, DOI 10.1145/2024716.2024718
[10]   SPACE/TIME TRADE/OFFS IN HASH CODING WITH ALLOWABLE ERRORS [J].
BLOOM, BH .
COMMUNICATIONS OF THE ACM, 1970, 13 (07) :422-&