A Low-Power Low-Phase-Noise CMOS VCO using RF SiP Technology

被引：0
|
作者：
Ohashi, Kazuma [1 ]
Ito, Yusaku [1 ]
Ito, Hiroyuki [2 ]
Okada, Kenichi [1 ]
Hatakeyama, Hideki [3 ]
Ozawa, Naoyuki [3 ]
Sato, Masakazu [3 ]
Aizawa, Takuya [3 ]
Ito, Tatsuya [3 ]
Yamauchi, Ryozo [4 ]
Masu, Kazuya [1 ]
机构：
[1] Tokyo Inst Technol, Integrated Res Inst, Midori Ku, 4259-R2-17 Nagatsuta, Yokohama, Kanagawa 2268503, Japan
[2] Tokyo Inst Technol, Precis & Intelligent Lab, Midori Ku, 4259-R2-17 Nagatsuta, Yokohama, Kanagawa 2268503, Japan
[3] Fujikura Ltd, Elect Device Lab, Chiba 2858550, Japan
[4] Fujikura Ltd, Chiba 1358512, Japan
来源：
2007 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5 | 2007年
关键词：
RF SiP technology; high-Q inductor; LC-VCO; low power; low phase noise; CMOS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a feasibility study on VCO using RF SiP technology, which is an RF application of stacked SiP, An off-chip inductor is implemented in a separated chip, and measured Q factor is 130. A phase noise is -119 dBc/Hz at 1 MHz offset for a 5.84-GHz carrier frequency, and frequency tuning range is 5.73 GHz-5.95 GHz. Power consumption is 1.93 mW, and 180 nm CMOS process is utilized. FOM is -192 dBc/Hz.
引用
收藏
页码：1963 / +
页数：2
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