Work-In-Progress: A Deep Learning Strategy for I/O Scheduling in Storage Systems

被引:4
作者
Farhangi, Ashkan [1 ]
Bian, Jiang [1 ]
Wang, Jun [1 ]
Guo, Zhishan [1 ]
机构
[1] Univ Cent Florida, Dept Elect & Comp Engn, Orlando, FL 32816 USA
来源
2019 IEEE 40TH REAL-TIME SYSTEMS SYMPOSIUM (RTSS 2019) | 2019年
基金
美国国家科学基金会;
关键词
D O I
10.1109/RTSS46320.2019.00066
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Under the big data era, there is a crucial need to improve the performance of storage systems for data-intensive applications. Data-intensive applications tend to behave in a predictable manner, which can be exploited for improving the performance of the storage system. At the storage level, we propose a deep recurrent neural network that learns the patterns of I/O requests and predicts the upcoming ones, such that memory contents can be pre-loaded at the right time to prevent cache/memory misses. Preliminary experimental results, on two real-world I/O logs of storage systems (from financial and web search), are reported-they partially demonstrate the effectiveness of the proposed method.
引用
收藏
页码:568 / 571
页数:4
相关论文
共 13 条
[1]   EC-Store: Bridging the Gap Between Storage and Latency in Distributed Erasure Coded Systems [J].
Abebe, Michael ;
Daudjee, Khuzaima ;
Glasbergen, Brad ;
Tian, Yuanfeng .
2018 IEEE 38TH INTERNATIONAL CONFERENCE ON DISTRIBUTED COMPUTING SYSTEMS (ICDCS), 2018, :255-266
[2]  
[Anonymous], 2014, Advances in neural information processing systems
[3]   Vectorizing disks blocks for efficient storage system via deep learning [J].
Dai, Dong ;
Bao, Forrest Sheng ;
Zhou, Jiang ;
Shi, Xuanhua ;
Chen, Yong .
PARALLEL COMPUTING, 2019, 82 :75-90
[4]  
Gers Felix A, 1999, LEARNING FORGET CONT
[5]  
Gill BS, 2005, USENIX ASSOCIATION PROCEEDINGS OF THE GENERAL TRACK: 2005 UNENIX ANNUAL TECHNICAL CONFERENCE, P293
[6]  
Hashemi M., 2018, LEARNING MEMORY ACCE
[7]  
Li Jiwei, 2015, VISUALIZING UNDERSTA
[8]  
Li ZM, 2004, USENIX ASSOCIATION PROCEEDINGS OF THE 3RD USENIX CONFERENCE ON FILE AND STORAGE TECHNOLOGIES, P173
[9]   3D-Stacked memory architectures for multi-core processors [J].
Loh, Gabriel H. .
ISCA 2008 PROCEEDINGS: 35TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, 2008, :453-464
[10]  
Moore G.E., 1965, Cramming More Components onto Integrated Circuits