Towards the Least Complex Time-Multiplexed Constant Multiplication

被引:0
作者
Aksoy, Levent [1 ]
Flores, Paulo [2 ]
Monteiro, Jose [2 ]
机构
[1] INESC ID, Lisbon, Portugal
[2] IST TU Lisbon, INESC ID, Lisbon, Portugal
来源
2013 IFIP/IEEE 21ST INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC) | 2013年
关键词
ALGORITHM; BLOCKS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The multiplication of a variable by a single constant selected from a set of fixed constants at a time, called the time-multiplexed constant multiplication (TMCM), is frequently used in digital signal processing (DSP) systems. Existing algorithms implement the TMCM operation using multiplexers (MUXes), adders/subtractors, and shifts, and reduce its complexity by merging single/multiple constant multiplication graphs and by sharing the basic structures. This paper introduces ARION, that exploits the most common partial terms in the TMCM design on top of the previously proposed DAGfusion algorithm, which merges the single constant multiplication graphs. Experimental results show that ARION obtains significantly better solutions than prominent TMCM methods.
引用
收藏
页码:328 / 331
页数:4
相关论文
共 11 条
[1]   Exact and approximate algorithms for the optimization of area and delay in multiple constant multiplications [J].
Aksoy, Levent ;
Da Costa, Eduardo ;
Flores, Paulo ;
Monteiro, Jose .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, 27 (06) :1013-1026
[2]  
Barth P., 1995, TECH REP
[3]   High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier [J].
Chen, Jiajia ;
Chang, Chip-Hong .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, 28 (12) :1844-1856
[4]   Reconfigurable multiplier blocks: Structures, algorithm and applications [J].
Demirsoy, Sueleyman Sirri ;
Kale, Izzet ;
Dempster, Andrew .
CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2007, 26 (06) :793-827
[5]   USE OF MINIMUM-ADDER MULTIPLIER BLOCKS IN FIR DIGITAL-FILTERS [J].
DEMPSTER, AG ;
MACLEOD, MD .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1995, 42 (09) :569-577
[6]  
Gustafsson O, 2002, 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, PROCEEDINGS, P73
[7]   A heuristic approach for multiple restricted multiplication [J].
Sidahao, N ;
Constantinides, GA ;
Cheung, PYK .
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, :692-695
[8]  
Sidahao N, 2004, LECT NOTES COMPUT SC, V3203, P374
[9]   Time-multiplexed multiple-constant multiplication [J].
Tummeltshammer, Peter ;
Hoe, James C. ;
Pueschel, Markus .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (09) :1551-1563
[10]   Highly efficient, limited range multipliers for LUT-based FPGA architectures [J].
Turner, RH ;
Woods, RF .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (10) :1113-1117