Integrated circuit implementation of a compact discrete-time chaos generator

被引：35

作者：

Juncu, V ^{[1
]}

Rafiei-Naeini, M ^{[1
]}

Dudek, P ^{[1
]}

机构：

[1] Univ Manchester, Sch Elect & Elect Engn, Manchester M60 1QD, Lancs, England

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2006年 / 46卷 / 03期

关键词：

map circuit; chaos generator; bifurcation diagram; Lyapunov exponent; random noise generator;

D O I：

10.1007/s10470-006-1432-0

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A discrete-time chaos generator implemented with two nonlinear circuit cells has been fabricated in a 0.6 mu m CMOS technology. Each cell is creating a function (map) which allows a chaos signal to be generated. Measurements of the chip were performed with a supply voltage of 5 V, up to a frequency of 2.5 MHz. A bifurcation diagram of the circuit and the Lyapunov exponent calculation are presented. The size of the generator layout (without the switches) is 32 x 19 mu m which makes it suitable for applications where many chaos signal generators are required on a single chip.

引用

页码：275 / 280

页数：6

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