Time Delay Model for SRAM Compiler

被引：0

作者：

Sonq, Qiang ^{[1
]}

Peng, Chunyu ^{[1
]}

Zhou, Honggang ^{[1
]}

Tan, Shoubiao ^{[1
]}

机构：

[1] Anhui Univ, Sch Elect & Informat Engn, Hefei 230601, Anhui, Peoples R China

来源：

MECHATRONICS, ROBOTICS AND AUTOMATION, PTS 1-3 | 2013年 / 373-375卷

关键词：

Time delay; Tcq; model; decoder; word line; bit line;

D O I：

10.4028/www.scientific.net/AMM.373-375.1561

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we introduced an effective time delay model for SRAM compiler, which represents an important performance of SRAM. Our method divide the delay time into several periods, including decoder delay, word line delay, bit line delay and SA delay. The theory is useful in predicting the delay time when the SRAM size is changed. Simulations by Hsim in 65nm CMOS process proves a high accuracy.

引用

页码：1561 / 1566

页数：6

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