STUDY OF JITTER GENERATORS FOR HIGH-SPEED I/O INTERFACE JITTER TOLERANCE TESTING

被引：0

作者：

Ozawa, Yuki ^{[1
]}

Arafune, Takuya ^{[1
]}

Tsukiji, Nobukazu ^{[1
]}

Kobayashi, Haruo ^{[1
]}

Shiota, Ryoji ^{[2
]}

机构：

[1] Gunma Univ, Grad Sch Sci & Technol, Div Elect & Informat, Kiryu, Gunma 3768515, Japan

[2] Socionext Inc, Kohoku Ku, Nomura Shin Yokohama Bldg,2-10-23 Shin Yokohama, Yokohama, Kanagawa 2220033, Japan

来源：

2017 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS 2017) | 2017年

关键词：

Jitter Generation; Jitter Tolerance Testing; High-Speed I/O Interface; Inter-Symbol Interference; Delta-Sigma Modulation;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper proposes two low-cost jitter generators for highspeed I/O interface jitter tolerance testing. (i) The first one uses inter-symbol interference positively with digital control. The proposed circuit consists of mostly digital circuits with small amount of analog circuits (simple RC low-pass filter), and the digital part can be realized using FPGA or high-speed digital unit of an automated test equipment (ATE). (ii) The second one uses a digital Delta Sigma modulator with some amount of analog circuits, and the digital part can be realized using highspeed digital unit of the ATE; the digital modulator can be realized by software on the ATE, and its output controls switches in the analog circuits. Their principles, theoretical analyses and simulation results are presented.

引用

页码：468 / 473

页数：6