STUDY OF JITTER GENERATORS FOR HIGH-SPEED I/O INTERFACE JITTER TOLERANCE TESTING

This paper proposes two low-cost jitter generators for highspeed I/O interface jitter tolerance testing. (i) The first one uses inter-symbol interference positively with digital control. The proposed circuit consists of mostly digital circuits with small amount of analog circuits (simple RC low-pass filter), and the digital part can be realized using FPGA or high-speed digital unit of an automated test equipment (ATE). (ii) The second one uses a digital Delta Sigma modulator with some amount of analog circuits, and the digital part can be realized using highspeed digital unit of the ATE; the digital modulator can be realized by software on the ATE, and its output controls switches in the analog circuits. Their principles, theoretical analyses and simulation results are presented.