3D Electro-Thermal Modeling for ESD protection structures in Sub-100nm CMOS

被引：0
|
作者：
Lin, L. [1 ]
Wang, X. [1 ]
Liu, J. [2 ]
Wang, A. [1 ]
Liu, H. [3 ]
Zhou, Y. [3 ]
Yang, L. [4 ]
机构：
[1] Univ Calif Riverside, Dept Elect Engn, Riverside, CA 92521 USA
[2] Tsinghua Univ, Beijing, Peoples R China
[3] Chinese Acad Sci, Inst Microelect, Beijing, Peoples R China
[4] SMIC, Shanghai, Peoples R China
来源：
2008 2ND IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE, VOLS 1-3 | 2008年
关键词：
D O I：
10.1109/INEC.2008.4585540
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper reviews advances in new 3D electro-thermal modeling technique for ESD (electrostatic discharge) protection structures. New 3D ESD device modeling is critical to full-chip ESD protection circuit design synthesis, verification, optimization and prediction, especially for IC designs in sub-100mn CMOS technologies.
引用
收藏
页码：520 / +
页数：2
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