A Power-Efficient Receiver Architecture Employing Bias-Current-Shared RF and Baseband With Merged Supply Voltage Domains and 1/f Noise Reduction

A power-efficient quadrature receiver employing a down-converter that uses a passive current-commutating mixer for frequency translation is presented. The architecture uses bias-current sharing between the RF and baseband stages while making the full supply voltage available to either stage. An input transconductor, realized using a differential common-source stage, converts the RF signal into a current, while baseband amplification is achieved using a transimpedance amplifier. Active noise shaping networks are implemented for reducing low-frequency noise at the output that can arise from the RF and baseband transconductors. Linearity is enhanced by synthesizing a nonlinear gain in the transimpedance amplifier to compensate for baseband compression. The design includes variable gain capability. An on-chip divider is employed to synthesize quadrature LO signals. Noise and linearity performance of the core down-converter is analyzed. The receiver is implemented in a 0.18 mu m CMOS technology. The prototype achieves a maximum conversion gain of 44.5 dB, NF of 4.3 dB, in-channel OIP3 of 20 dBV while consuming 2.2 mA in each of the quadrature paths from a 1.8 V supply. This performance is achieved without the use of integrated inductors, which allows for a small die area of 0.5 mm(2).