Comparison of Thermal Stress Concentration and Profile between Power Cycling Test and Thermal Cycling Test for Power Device Heat Dissipation Structures using Ag Sintering Chip-attachment

Power semiconductor device technology needs highly efficient heat dissipation system having a chip bonding layer with high thermal conductance and reliability. This work clarifies 3D thermal stress profiles under power cycling test (PCT) and thermal cycling test (TCT) with multi-physics solver for the system having Ag sintered bonding layer as a new chip attachment technology. Both reliability test results on Von Mises stress profile are compared and the key features for each test are made clear. It was found that the maximum stress values within Si chip and Ag sintered bonding layer are at the corner of bonding layer for both PCT and TCT. The maximum stress of bonding layer under PCT ON state at chip power of 400 W is lower than the value under TCT with Ta of 25. which is the Ta of PCT. Under PCT the temperature difference from stress free temperature (Tr) for bonding layer is smaller than that under TCT with Ta of 25., and this results in lower thermal stress in bonding layer. The maximum stress value of Ag sintered layer is a little lower than the conventional solder value under both PCT and TCT. This smaller stress of Ag sintered layer is thought to be due to lower Young's modulus of the Ag sintered layer.