Error identification in at-speed scan BIST environment in the presence of circuit and tester speed mismatch

被引：2
作者：
Nakamura, Y [1 ]
Clouqueur, T
Saluja, KK
Fujiwara, H
机构：
[1] Nara Inst Sci & Technol, Ikoma 6300192, Japan
[2] NEC Elect Corp, Kawasaki, Kanagawa 21118666, Japan
[3] Univ Wisconsin, Madison, WI USA
来源：
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | 2006年 / E89D卷 / 03期
关键词：
BIST; fault diagnosis; error identification; at-speed test; low speed tester;
D O I：
10.1093/ietisy/e89-d.3.1165
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
tit this paper, we provide a practical formulation of the problem of identifying all error occurrences and all failed scan cells in at speed scan based BIST environment. We propose a method that can be used to identify every error when the circuit test frequency is higher than the tester frequency. Our approach requires very little extra hardware for diagnosis and the test application time required to identify errors is a linear function of the frequency ratio between the cur and the tester.
引用
收藏
页码：1165 / 1172
页数：8
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