Metal capacitor technology for application to merged DRAM logic devices

Recently there has been a surge in development of DRAM-embedded ASICs and other System-on-a-Chip (SOC) devices. Considering a high-performance CMOS process as a base into which DRAM is to be embedded or merged, it is necessary to substantially reduce the process temperatures used to fabricate storage capacitors and other structures in the DRAM:memory cell. Polysilicon-Insulator-Polysilicon (PIP) type capacitor technology currently used in commodity DRAMs requires process temperatures above 750 degrees C, which exceeds the 650 degrees C thermal budget limit of 0.18 mu m CMOS devices. To address this process divergence, NEC has developed a Metal-Insulator-Metal (MIM) type capacitor technology, using, Ta2O5, and TiN, that ensures DRAM compatibility with the surrounding on-chip logic. The process issues and specific electrical results demonstrating the feasibility of this metal capacitor technology are reported herein.