Inelastic Electron Tunneling Spectroscopy (IETS) Study of Ultra-thin Gate Dielectrics for Advanced CMOS Technology

As the thickness of the gate dielectric in a CMOS transistor continues to shrink in each new generation of integrated circuits in order to meet the targeted gains in performance and circuit density, it becomes increasingly difficult for some conventional dielectric characterization tools, such as infrared spectroscopy, Raman spectroscopy, neutron scattering, and Rutherford scattering, to reveal their structural and compositional information. In contrast, the Inelastic Electron Tunneling Spectroscopy (IETS) technique, which relies on tunneling current to probe the ultra-thin gate dielectric in a metal-insulator-semiconductor (MIS) sandwich, becomes more sensitive when the tunneling current increases, which is in the direction of the CMOS scaling trend. IETS can address materials issues related to reactions and intermixing at interfaces, as well as properties related to carrier mobility and reliability, such as phonon modes, impurities, and charge traps, for structures that are difficult to accurately characterize by other techniques. The principle of operation, experimental considerations, and examples will be shown in this paper to illustrate the capabilities and limitations of the IETS technique.